Transaction Level Modeling (TLM) for communication between verification components.A reporting mechanism for a consistent way of printing and logging results.Verification phases for synchronizing concurrent processes.A factory for constructing objects and substituting objects.A library of base classes for building testbench components ( Agent, Sequencer, Driver, Monitor, Scoreboards, Environment class etc). UVM is an open source code that provides: One can think of UVM as a pre-defined verification testbench architecture which is re-usable, scalable and configurable. It has been jointly defined by Synopsys, Mentor Graphics, Cadence and end users. User can download UVM UserGuide by Acellera here and UVM source code can be downloaded from Acellera website. UVM stands for Universal Verification Methodology and was created by an organization called “Accellera”. UVM is based on OVM plus key features from VMM and TLM(by Open SystemC Initiative). It is an IEEE standard/methodology based on System Verilog language. UVM is a Standard Verification Methodology which uses System Verilog constructs based on which a fully functional testbench can be built to verify functional correctness of Design Under Test(DUT). This section is an introduction to UVM and we will soon know what is UVM and its key features.
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December 2022
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